Report: Arm cancels Qualcomm’s instruction set, IP license for chip design

The dispute between Qualcomm and Arm has escalated with the latter canceling Qualcomm’s ability to use the instruction set for designing chips. 

According to Bloomberg today, Arm is “canceling a license that allowed longtime partner Qualcomm Inc. to use Arm intellectual property to design chips.” If there’s no resolution after the 60-day notice period, Qualcomm “might have to stop selling products… or face claims for massive damages.” Specifically:

If Arm follows through with the license termination, Qualcomm would be prevented from doing its own designs using Arm’s instruction set. It would still be able to license Arm’s blueprints under separate product agreements, but that path would cause significant delays and force the company to waste work that’s already been done.

Since 2022, Arm has been fighting Qualcomm, which countersued, over its purchase of a company (Nuvia) that resulted in Oryon CPUs, which are coming soon to mobile SoCs and automotive after debuting for Windows laptops. Instead of using Arm’s Cortex cores in the CPU, Qualcomm now has its own custom design.

When the acquisition took place, Arm argued that what Nuvia created as an Arm licensee cannot be transferred to Qualcomm without permission or contract renegotiation, and that designs should be destroyed.  

Qualcomm argues that its existing agreement covers the activities of the company that it purchased, the chip-design startup Nuvia.

It would seem that SoCs with Oryon CPUs — Snapdragon X Elite, which is already on the market in various PCs, and Snapdragon 8 Elite — will be impacted, while earlier models (e.g., Snapdragon 8 Gen 3) remain available.

It remains to be seen whether Qualcomm and Arm will come to agreement within 60 days.

Looking ahead, this Arm uncertainty could lead to the adoption of the open source RISC-V instruction set. Back in October of 2023, Qualcomm and Google announced work on a RISC-V Wear OS chip. The Android team is actively working on adding OS support with a focus on ensuring that “any CPU running RISC-V will have all of the features we expect to achieve high performance.”